PhD studentship: mapping SYCL (C++) to FPGA architectures

by Rob Stewart, March 1, 2019

Two key requirements for real time decision making in robotics systems and smart sensors are 1) increased compute power for intelligent autonomy, and 2) energy efficiency for long-lasting operation. FPGAs are an ideal fit, but are notoriously difficult to program.

This PhD project will develop hardware cost modelling and compiler optimisation techniques to map SYCL, a C++ standard for heterogeneous computing, down to programmable FPGAs. The goal is to support the generation of extremely efficient application specific processors from high level C++, for autonomous devices and smart sensors.

The PhD will be an industrial collaboration between Codeplay and Dr Robert Stewart at Heriot-Watt University in Edinburgh.

Application deadline: 17th March.

Computing platforms for robotics, smart sensors, and remote autonomous AI are constructed from diverse computing components with diverse performance and power requirements. A typical platform combines multicore CPUs/GPUs and, increasingly, FPGAs for specialised close-to-sensor processing.

The performance metric for a particular autonomous robotics system may be accuracy, latency, energy use, throughput, or any combination of these. To meet these requirements, a major challenge is the seamless realisation of some given computation across different configurations of processing components. This is made harder by major differences in programming models for such components and the lack of common abstractions and toolsets.

In particular, FPGAs are very low powered accelerated processors, which are ideal for remote computation where access to power and network connectivity is limited, e.g. where autonomously deployed devices and sensors cannot transmit raw data. Application areas exploitable with FPGAs include smart CCTV surveillance, autonomous vehicles and medical diagnosis.

The major drawback of FPGAs is programmability. They are notoriously difficult and time consuming to engineer and debug, holding back their wider adoption with the software industry, roboticists, and manufacturers of heterogeneous processing hardware.

This PhD project, supported by Codeplay and the Robotics and Autonomous Systems CDT, will address this challenge by combining Heriot-Watt University's programming language and FPGA research, with Codeplay's architectures and compilers expertise.

The RAS-CDT PhD student will work with Codeplay on an FPGA implementation of the SYCL open standard. Codeplay's image processing DSL, VisionCPP, will serve as an excellent case study for demonstrating high level programming for parallel image processing on heterogeneous platforms, in particular on low powered FPGAs via the proposed SYCL FPGA backend.

Application deadline: 17th March.

More information:


Application process:

Dr Robert Stewart's web pages:

Please contact me at [email protected] if you want more information.