2nd CFPs: Constraint​​s in Formal Verificati​​on 2011

Overview
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Formal verification is of crucial significance in the development of
hardware and software systems. In the last few years, tremendous
progress was made in both the speed and capacity of constraint
technology. Most notably, SAT solvers have become orders of magnitude
faster and capable of handling problems that are orders of magnitude
bigger, thus enabling the formal verification of more complex computer
systems. As a result, the formal verification of hardware and software
has become a promising area for research and industrial applications.
The main goals of the Constraints in Formal Verification workshop are
to bring together researchers from the CSP/SAT and the formal
verification communities, to describe new applications of constraint
technology to formal verification, to disseminate new challenging
problem instances, and to propose new dedicated algorithms for hard
formal verification problems.
This workshop will be of interest to researchers from both academia
and industry, working on constraints or on formal verification and
interested in the application of constraints to formal verification.


Scope
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The scope of the workshop includes topics related to the application
of constraint technology to formal verification, namely:
- application of constraint solvers to hardware verification;
- application of constraint solvers to software verification;
- dedicated solvers for formal verification problems;
- challenging formal verification problems.


Submissions
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Submissions should be in the IEEE format and in one of the following types:
- a regular paper of up to 6 pages;
- a short paper of up to 4 pages, describing an industrial experience.
Workshop papers should be submitted electronically in pdf format.
Abstract and paper submissions should be e-mailed to the workshop chair at: [email protected]


Important Dates
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- abstract submission deadline:  September 25, 2011
- paper submission deadline:  September 30, 2011
- notification of acceptance:  October 10, 2011
- camera-ready version deadline: October 25, 2011
- workshop date:  November 10, 2011

Invited Speaker
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Carl Seger, Intel, U.S.A.

Natarajan Shankar, SRI, U.S.A.

Workshop Chair
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Miroslav Velev, Aries Design Automation, U.S.A.

Program Committee
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Maciej Ciesielski, University of Massachusetts, U.S.A.

Masahiro Fujita, University of Tokyo, Japan

Alex Groce, Oregon State University, U.S.A.

Daniel Grosse, University of Bremen, Germany

Michael Hsiao, Virginia Tech, U.S.A.

Sumit Jha, University of Central Florida, U.S.A.

Robert Jones, Intel, U.S.A.

Peter-Michael Seidel, AMD, U.S.A.

Andreas Veneris, University of Toronto, Canada

Markus Wedler, University of Kaiserslautern, Germany